Clock

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Clock

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Signal\Logical\Discrete

Use

Domains: Continuous. Size: 1-D. Kind: Block Diagrams.

Description

This models generates a logical discrete clock signal, i.e. a signal that changes from true (1) to false (0) and vice-versa, each sample time.

Clock-Discrete

Interface

Outputs

Description

output

 

Parameters

 

initial

T

Initial value of the output.

Clock-period.