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Navigation: Library > Signal > Logical > Continuous > Clock |
  
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Signal\Logical\Continuous
Domains: Continuous. Size: 1-D. Kind: Block Diagrams.
This models generates a logical continuous clock signal, i.e. a signal that changes from true (1) to false (0) and back, each period T.
Outputs |
Description |
output |
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Parameters |
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initial T |
Initial value of the output. Clock-period. |